\doxysubsubsubsection{RCCEx I2\+C1 Clock Source }
\hypertarget{group___r_c_c_ex___i2_c1___clock___source}{}\label{group___r_c_c_ex___i2_c1___clock___source}\index{RCCEx I2C1 Clock Source@{RCCEx I2C1 Clock Source}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
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\Hypertarget{group___r_c_c_ex___i2_c1___clock___source_gaf15b7facb255a4bb9d83c2b3c282bea9}\label{group___r_c_c_ex___i2_c1___clock___source_gaf15b7facb255a4bb9d83c2b3c282bea9} 
\#define {\bfseries RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+D2\+PCLK1}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+D2\+PCLK1
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\Hypertarget{group___r_c_c_ex___i2_c1___clock___source_ga5b19521d83bbca302b707f97076786ba}\label{group___r_c_c_ex___i2_c1___clock___source_ga5b19521d83bbca302b707f97076786ba} 
\#define {\bfseries RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+PLL3}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+PLL3
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\Hypertarget{group___r_c_c_ex___i2_c1___clock___source_ga5645524b292048cfe127da02ba9b3df7}\label{group___r_c_c_ex___i2_c1___clock___source_ga5645524b292048cfe127da02ba9b3df7} 
\#define {\bfseries RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+HSI}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+HSI
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\Hypertarget{group___r_c_c_ex___i2_c1___clock___source_gab441e477902a86bf58356e078e50b074}\label{group___r_c_c_ex___i2_c1___clock___source_gab441e477902a86bf58356e078e50b074} 
\#define {\bfseries RCC\+\_\+\+I2\+C1\+CLKSOURCE\+\_\+\+CSI}~RCC\+\_\+\+I2\+C123\+CLKSOURCE\+\_\+\+CSI
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
